1. Technical Field
The present invention relates to integrated circuits and, more particularly, to improve interconnects.
2. Description of Related Art
In modern integrated circuits, interconnect (wire) delays are rapidly becoming more of a problem. As technology improves and chip dimensions shrink, transistors are getting faster, but resistance and capacitance of wires are not improving as quickly. As a result, the interconnect delays are rapidly becoming the critical design constraint, preventing chips from operating at higher frequencies. Current art recommends increasing the width of the interconnects, thus reducing their resistance, or spacing the interconnects further apart, reducing the effects of capacitive coupling with neighboring interconnects. However, both of these courses of action utilize more wiring resources than is desirable. In all cases there is some limit to the amount of width and spacing growth that can be done. This problem is especially bad for signal busses which frequently must travel from one side of a chip to the other. Periodically repeater circuits must be placed along a bus""s path to repower the signals, because the resistance and capacitance of the interconnect has degraded the signal quality. Each interconnect wire will have two neighboring interconnects on the same metal layer. A wire can be affected by its neighbors in the following ways: Hostilexe2x80x94Neighbor is switching in the opposite direction; Friendlyxe2x80x94Neighbor is switching in the same direction; Quietxe2x80x94Neighbor is not switching.
If both neighbors are switching in the opposite direction the signal of interest is switching, a signal is said to have two xe2x80x9chostile neighborsxe2x80x9d. This hostility can significantly increase the amount of time required for a signal to propagate along its path. In other words, it slows down the speed of signal propagation. Current methods of reducing effects of hostility include increasing the space between potentially hostile wires, increasing the width of wires (to reduce resistance), or inserting an additional quiet wire (a xe2x80x9cshieldxe2x80x9d) between each pair of signal wires. This invention is better, because it makes more efficient use of the precious wiring resources available on chips. Increasing wires widths and spacings means that fewer wires can fit in a given area. Similarly inserting quiet wires between signal wires also uses resources which otherwise could be used for other integrated circuit components. Therefore, it would be desirable to have an improved integrated circuit interconnect design that reduces hostile coupling while improving the speed of performance and minimizing die space usage by the interconnect.
The present invention provides a bus having improved performance over prior art busses. In one embodiment, the bus includes a first wire having a plurality of intervals, a second wire having a plurality of intervals, and a third wire having a plurality of intervals. The first, second, and third wires are intertwined with each other. Some intervals of the wires include a buffer and some other intervals of the wires include an inverter. In some embodiments, the intervals of the wires that include the buffer are middle wires and in other embodiments, the intervals of the wires the include the buffer are outer wires.